In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on a substrate, such as a semiconductor wafer. For example, the integrated circuits are formed by multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions and gate electrode conductors are farmed. In higher levels above the substrate level, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive structures/layers are insulated from other conductive structures/layers by dielectric materials.
As part of the semiconductor device fabrication process, plasma etching processes are often utilized to remove selected materials previously deposited on the substrate so as to pattern, shape, or otherwise manipulate the materials on the substrate into structures needed to form part of the integrated circuit device. The plasma etching process involves generation of a plasma, including reactive constituents such as radicals and ions, and exposure of the substrate to the radicals and ions of the plasma in a controlled manner. It is within this context that the present invention arises.